This results in efficient data transfers for some slave devices. When the microprocessor is connected to a slave device that has both input and output capability using SPI, as data is clocked out of the master, data is also clocked in from the slave device. Daisy chain multiple slave SPI bus configuration with a common device select signal. Parallel multiple slave SPI bus configuration with individual device select signals.įigure 5.2. Due to the excessive data transfer time for systems with many slave devices, this configuration is seldom used.įigure 5.1. This additional data transfer time is the cost of conserving processor I/O pins used for enabling slave devices. Data that is to be read from the first slave device in the chain must also be clocked through the slave devices that follow it in the chain. Using this configuration, data intended for the last device in the chain must be clocked through the preceding slave devices. This is the more common SPI connection configuration.įigure 5.2 shows a daisy-chain configuration where slave devices share both the SCK and SS signals, and the MOSI and MISO signals are routed through a series of slave devices. For this connection configuration, the slave devices are explicitly selected by multiple dedicated SS microprocessor outputs. Figure 5.1 shows that the multiple slave devices share SCK, MOSI, and MISO signals. Other than the clock signal, all handshaking is handled by an explicit slave select (SS) or chip select ( CS) signal.įigures 5.1 and 5.2 illustrate the two common SPI bus connection configurations. The slave devices are able to send data to the master over the Master In Slave Out ( MISO) line. The master writes data to the slave using the Master Out Slave In ( MOSI) line. SPI requires four wires for full-duplex operation and supports only one master but multiple slave devices. The master device has exclusive control of the serial clock (SCK) signal that is used to clock the data to and from a slave device. As with the I2C protocol, the SPI bus implements a master-slave communications scheme where the master device alone controls the data exchange with slave devices. SPI is a full-duplex synchronous serial communications bus protocol developed by Motorola and has become a de facto standard that has not been adopted by any national or international standards organizations. Unlike I 2C, SPI has no device acknowledge capability. Although I 2C requires only two wires (thus conserving processor pins), rather than four wires required by SPI, I 2C has bandwidth overhead due to the time required for device selection by sending the ID as a serial byte. The SPI serial protocol is capable of higher data rates than I2C because it can generally operate at higher clock rates, and is not limited to 8-bits per word.
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